EPM570FGF256I5N vs EPM570F256I5 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM570FGF256I5N sa pamamagitan ng Intel at EPM570F256I5 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM570FGF256I5N | EPM570F256I5 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | NRND |
| Family | MAX II | MAX II |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Elements (LEs) | 570 | — |
| Macrocells | 440 | — |
| Propagation Delay (tPD) | 5.0 ns | — |
| User I/O Pins (max) | 212 | — |
| Packhaging | 256-ball FBGA (FGF256) | — |
| Process Technology | 0.18 micron | — |
| Configuration Memory | Internal Flash (non-volatile, instant-on) | — |
| Programming Interface | JTAG / ISP | JTAG (IEEE 1149.1) / ISP |
| Volte ng Pagbibigay | 3.3 V core / multi-volt I/O (1.5/1.8/2.5/3.3 V) | — |
| Temperature Grade | Industrial (-40C to +100C) | — |
| Speed Grade | 5 (fast) | I5 |
| Temperature na Operasyon | -40C to +100C | -40C to +85C (industrial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | Compliant | [DATA_NEEDED: RoHS status] |
| Logic Elements (LE) | — | 570 |
| Maximum User I/O Pins | — | 160 |
| User Flash Memory (UFM) | — | 8 Kbits |
| Number of LABs/CLBs | — | [DATA_NEEDED: number of LABs] |
| Package Type | — | 256-ball FineLine BGA (FBGA-256) |
| Supply Voltage - Core | — | 3.3 V (also operates at 3.3V per part description) |
| I/O Standards Supported | — | LVTTL, LVCMOS, SSTL, PCI |
| MultiVolt I/O | — | 1.5V / 1.8V / 2.5V / 3.3V |
| In-System Programmability | — | Yes |
| Non-volatile Configuration | — | Yes (on-chip flash) |
| Pin-to-Pin Logic Delay (typ) | — | 5 ns to 7 ns |
| Maximum Internal Frequency | — | [DATA_NEEDED: fMAX MHz per speed grade] |
| Number of PLLs | — | [DATA_NEEDED: number of PLLs] |
| Width | — | 17 mm (per Partstack) |