EPM570GF100C5N vs EPM570F100C4N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM570GF100C5N sa pamamagitan ng Altera at EPM570F100C4N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM570GF100C5N | EPM570F100C4N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Device Family | MAX II | — |
| Logic Elements | 570 | 440 LE |
| Macrocells | 440 | 440 |
| User I/Os | 76 | — |
| Propagation Delay (tPD) | 5.4 ns | — |
| Packhaging | 100-LBGA (FBGA-100), 11 x 11 mm, 1.0 mm pitch | 100-FBGA (FineLine BGA) 11 mm x 11 mm |
| Configuration Memory | On-chip Flash (non-volatile) | — |
| Core Voltage | 1.8 V (internal) | — |
| I/O Voltage Support | 1.8 V / 2.5 V / 3.3 V (5.0 V tolerant inputs) | — |
| Temperature na Operasyon | -40C to +125C (industrial) | 0 C to +85 C (commercial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Programming Interface | IEEE 1532 / JTAG (IEEE 1149.1) ISP | — |
| Tindminan RoHS | Compliant (lead-free) | — |
| Logic Family / Process | CMOS, Flash-based LUT | — |
| LABs | 4 (16 macrocells per LAB) | — |
| Family | — | MAX II |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Maximum User I/O | — | 80 |
| Pin-to-Pin Delay (tPD1) | — | 5.4 ns |
| User Flash Memory | — | 4.4 Kbits |
| Configuration Technology | — | Flash (non-volatile, instant-on) |
| Operating Voltage (Core) | — | 3.3 V (internal regulator) |
| I/O Voltage Support (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |
| Hot Socketing | — | Yes |