EPM570GT100I5N vs EPM570GT100C5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM570GT100I5N sa pamamagitan ng Altera at EPM570GT100C5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM570GT100I5N - 440-Macrocell CPLD, 5.4ns, MAX II, 100-TQFP | Altera
EPM570GT100I5N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM570GT100I5N | EPM570GT100C5N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX II | — |
| Logic Elements | 570 LE | 570 |
| Equivalent Macrocells | 440 macrocells | 440 |
| Number of LABs | 57 | — |
| User I/Os | 76 | — |
| Maximum Operating Frequency | 304 MHz | — |
| Propagation Delay (tPD1) | 5.4 ns | — |
| Operating Supply Voltage (Core) | 1.8 V | — |
| User Flash Memory | 8 Kbit | — |
| Packhaging | 100-pin TQFP (GT100) | TQFP-100 |
| Uri ng Pagpapasok | Surface Mount (SMD/SMT) | Surface Mount |
| Temperature na Operasyon | -40 °C to +100 °C (Industrial) | 0C to +85C (Commercial) |
| Process | 0.18 µm, 6-layer-metal flash | — |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | IEEE 1149.1 boundary scan |
| MultiVolt I/O Support | 1.8 V / 2.5 V / 3.3 V | — |
| Internal Oscillator | Yes | — |
| Non-volatile Configuration | Yes (instant-on, no external boot PROM) | — |
| Tindminan RoHS | Compliant | Compliant |
| Series | — | MAX II |
| User I/O | — | 76 |
| LABs | — | 36 |
| Maximum Frequency | — | 304 MHz |
| Pin-to-Pin Delay | — | [DATA_NEEDED: tPD value] |
| User Flash Memory (UFM) | — | 8 Kbit |
| Operating Supply Voltage (VCCINT) | — | 2.5 V / 3.3 V |
| I/O Standards Supported | — | 1.5 V, 1.8 V, 2.5 V, 3.3 V LVTTL/LVCMOS |
| Programmability | — | Flash-based, non-volatile (ISP via JTAG) |