EPM570T100C3 vs EPM570T100C3N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM570T100C3 sa pamamagitan ng Intel at EPM570T100C3N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM570T100C3N - 440-Macrocell MAX II CPLD, 100-TQFP | Intel / Altera
EPM570T100C3N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM570T100C3 | EPM570T100C3N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX II | MAX II |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Elements | 570 | — |
| Equivalent Macrocells | 440 | — |
| User I/O Pins | 76 (max) | — |
| User Flash Memory (UFM) | 8 Kbits | 8 Kbits |
| Maximum Operating Frequency | 304 MHz | — |
| Technology Node | 0.18 µm 6-layer-metal flash process | — |
| Internal Supply Voltage | 2.5 V / 3.3 V | — |
| I/O Voltage Support (MultiVolt) | 1.5 V, 1.8 V, 2.5 V, 3.3 V | — |
| Packhaging | 100-pin TQFP (T100), 14×14 mm | 100-TQFP (T100) |
| Temperature Grade | Commercial (C) | — |
| Speed Grade | 3 (fastest C-grade) | C3 |
| Programming | In-System Programmable (ISP) via JTAG (IEEE 1149.1) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | Compliant | Compliant |
| Macro Cells | — | 440 |
| Logic Elements (LEs) | — | 570 |
| Maximum User I/Os | — | 76 |
| Pin-to-Pin Delay (tPD1) | — | 5.4 ns |
| Maximum Internal Frequency | — | 304 MHz |
| Number of LABs | — | 57 |
| Supply Voltage - Core | — | 2.5 V / 3.3 V |
| I/O Standards Supported | — | 1.5 V, 1.8 V, 2.5 V, 3.3 V (MultiVolt) |
| Process Technology | — | 0.18 µm Flash |
| Temperature na Operasyon | — | 0 °C to +85 °C (Commercial) |
| Programming Interface | — | JTAG / IEEE 1149.1 boundary-scan |
| In-System Programmable | — | Yes |