EPM570ZM256C7N vs EPM570ZM256C6N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM570ZM256C7N sa pamamagitan ng Altera at EPM570ZM256C6N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM570ZM256C7N | EPM570ZM256C6N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | MAX II Z | MAX II |
| Family | MAX II | — |
| Logic Elements (LE) | 570 | — |
| Macro Cells | 440 | — |
| User I/Os | 76 | 160 |
| User Flash Memory | 8 Kbits | 8 Kbits |
| Maximum Operating Frequency | 123.5 MHz | — |
| Pin-to-Pin Delay (tPD) | 5.0 ns | — |
| Core Supply Voltage | 1.71 V to 1.89 V (3.3 V with on-chip regulator) | — |
| I/O Supply Voltages | 1.5 V / 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| Process Technology | 0.18 µm CMOS | 0.18 micron CMOS, 6-layer-metal flash |
| Temperature na Operasyon | 0 °C to +85 °C (commercial) | 0C to +85C (commercial) |
| Packhaging | 256-ball MBGA (Micro FBGA), 0.5 mm pitch, 6 × 6 mm | 256-MBGA (FineLine BGA) 11x11 mm |
| Configuration Method | On-chip non-volatile (instant-on, ISP via JTAG) | — |
| JTAG Support | IEEE Std 1149.1 boundary-scan + ISP | — |
| Lead-Free / RoHS | Lead-free / RoHS compliant | — |
| Logic Family | CMOS | — |
| Logic Elements (LEs) | — | 570 |
| Macrocells | — | 440 |
| Pin/Pitch | — | 256 balls, 0.5 mm pitch (Heisener description) |
| Internal Core Voltage | — | 1.71 V to 1.89 V (1.8 V typical) |
| I/O Voltage Standards | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant |
| Propagation Delay (tPD) | — | 9 ns (per Heisener listing for Z speed grade) |
| Programmable Type | — | In System Programmable (Flash, non-volatile) |
| Uri ng Pagpapasok | — | Surface Mount (BGA) |
| Tindminan RoHS | — | Lead-free (per Heisener listing) |