EPM7096QC100-10 vs EPM7096LC68-7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7096QC100-10 sa pamamagitan ng Altera at EPM7096LC68-7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM7096QC100-10 - 96-Macrocell MAX 7000 CPLD, 10ns, PQFP-100 | Altera
EPM7096QC100-10 Obsolete
Pagsanggunian na paghahambing
| Parametro | EPM7096QC100-10 | EPM7096LC68-7 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 7000 | MAX 7000 |
| Macrocells | 96 | 96 |
| Logic Array Blocks | 4 | — |
| User I/O Pins | 76 | 52 |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Operating Frequency | 100 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Technology | EEPROM-based CMOS | — |
| Programming Interface | ByteBlaster / parallel (JTAG ISP on MAX 7000S variants) | — |
| Boundary Scan | IEEE Std. 1149.1 (JTAG) on MAX 7000S | — |
| PCI Compliance | Yes (PCI SIG Local Bus Specification Rev. 2.2 at -10 speed grade) | — |
| Temperature na Operasyon | 0 °C to +70 °C (commercial) | -40C to +85C (industrial, typical) |
| Packhaging | 100-pin PQFP (R-PQFP-G100, 20×14 mm, 0.65 mm pitch) | 68-pin J-Lead PLCC (LC68) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | Non-compliant (legacy 5V PLCC) |
| Device Type | — | CPLD (EEPROM-based) |
| Logic Array Blocks (LABs) | — | 4 |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| In-System Programming | — | Yes (IEEE 1149.1 JTAG) |
| Architecture | — | EEPROM, second-generation MAX |
| Global Clock Pins | — | 6 |
| Process Technology | — | CMOS EEPROM |