EPM7128AETC100-10 vs EPM7128AETI100-7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128AETC100-10 sa pamamagitan ng Intel at EPM7128AETI100-7 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM7128AETI100-7 - MAX 7000A CPLD, 128 Macrocells, 100-TQFP | Altera
EPM7128AETI100-7 ObsoletePagsanggunian na paghahambing
| Parametro | EPM7128AETC100-10 | EPM7128AETI100-7 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 7000A | MAX 7000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 | 128 |
| User I/Os | 84 | 84 |
| Usable Gates | 2.5K | 2,500 |
| Logic Array Blocks (LABs) | 8 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | 7.5 ns |
| Supply Voltage (Core) | 3.3 V | — |
| I/O Tolerance | 5.0 V tolerant | — |
| Program Technology | EEPROM (in-system programmable) | — |
| Packhaging | 100-pin TQFP (ET) | 100-pin TQFP (1.0 mm pitch, 14 x 14 mm) |
| Temperature na Operasyon | -40C to +85C (commercial/industrial) | -40 C to +85 C (Industrial) |
| JTAG Support | IEEE 1149.1 boundary-scan | Yes (IEEE 1149.1 boundary-scan) |
| Tindminan RoHS | Compliant | [DATA_NEEDED: confirm RoHS for non-N suffix] |
| Katayuan ng Lifecycle | Obsolete (migrate to MAX II or MAX V) | — |
| Logic Blocks (LABs) | — | 8 |
| Maximum Counter Frequency | — | 129.9 MHz |
| Supply Voltage - Core (VCCINT) | — | 3.3 V |
| I/O Bank Supply (VCCIO) | — | 2.5 V / 3.3 V / 5 V (MultiVolt) |
| Configuration Memory | — | EEPROM (non-volatile, in-system programmable) |
| Global Clock Inputs | — | 4 dedicated |
| Uri ng Pagpapasok | — | Surface Mount |
| Lead-Free Version (MPN Suffix) | — | -N suffix denotes lead-free (e.g., EPM7128AETI100-7N) |