EPM7128AETC144-7N vs EPM7128AETC144-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128AETC144-7N sa pamamagitan ng Altera at EPM7128AETC144-10N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM7128AETC144-7N - MAX 7000A CPLD, 128 Macros, 144-TQFP | Intel / Altera
EPM7128AETC144-7N ✓ NakahandaIntel
EPM7128AETC144-10N - MAX 7000A CPLD, 128 Macros, 144-TQFP | Intel
EPM7128AETC144-10N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM7128AETC144-7N | EPM7128AETC144-10N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX 7000A | MAX 7000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Gates | 2500 (2.5K gates) | 2,500 usable gates |
| Macro Cells | 128 | — |
| User I/Os | 36 (in 144-pin TQFP) | — |
| Maximum Operating Frequency | 129.9 MHz | — |
| Pin-to-Pin Delay | 7.5 ns | — |
| Propagation Delay (tpd) | 7.5 ns | — |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| Process Technology | CMOS, EEPROM-based | — |
| Programmability | In-System Programmable (ISP) via JTAG | — |
| Boundary-Scan Test | IEEE Std 1149.1 (JTAG) | — |
| Temperature na Operasyon | 0C to +70C (commercial) | 0 C to +70 C (commercial) |
| Packhaging | 144-pin TQFP | 144-pin TQFP (T144) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Pin-Compatible With | MAX 7000S 5.0V family (144-pin TQFP) | — |
| Tindminan RoHS | Compliant | [DATA_NEEDED: rohs status] |
| Lead-Free | Yes | [DATA_NEEDED: lead-free status] |
| Number of Macros | — | 128 |
| Number of I/O Pins | — | 100 (max user I/O) |
| Propagation Delay (tPD) | — | 10 ns (grade -10) |
| Internal Frequency | — | Up to 250 MHz |
| I/O Standards | — | 2.5 V / 3.3 V / 5 V multiVolt |
| Configuration Memory | — | CMOS EEPROM (non-volatile) |
| JTAG Support | — | IEEE 1149.1 compliant boundary-scan |