EPM7128AETI100-7N vs EPM7128ATI100-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128AETI100-7N sa pamamagitan ng Altera at EPM7128ATI100-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM7128AETI100-7N - MAX 7000A CPLD 128 Macro 84 I/O | Intel/Altera
EPM7128AETI100-7N ObsoleteAltera
EPM7128ATI100-10 - 128-Macrocell 10ns 3.3V CPLD | Altera MAX 7000A
EPM7128ATI100-10 ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EPM7128AETI100-7N | EPM7128ATI100-10 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Series | MAX 7000A | MAX 7000A |
| Family | MAX 7000A CPLD | MAX 7000A (MAX II of MAX 7000 series) |
| Macro Cells | 128 | — |
| Number of Usable Gates | 2,500 | — |
| Number of I/O | 84 | — |
| Number of Logic Array Blocks (LABs) | 8 | 4 |
| Propagation Delay (tPD max) | 7 ns | — |
| Maximum Operating Frequency (fCNT) | 129.9 MHz | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V | 3.0 V to 3.6 V (3.3 V typical) |
| I/O Bank Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (multi-volt I/O) | — |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| Packhaging | 100-pin TQFP (14x14 mm) | 100-pin TQFP (14x14 mm) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | -40C to +85C (Industrial) | -40C to +85C (Industrial, 'I' suffix) |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | — |
| Tindminan RoHS | Compliant | Non-compliant (legacy part) |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Programmable Type | — | EE PLD (EEPROM-based, in-system programmable) |
| Number of Macrocells | — | 128 |
| Usable Gates | — | 2,500 |
| Number of I/O Pins | — | 68 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Frequency (fMAX) | — | 87 MHz |
| I/O Standard | — | MultiVolt (2.5V / 3.3V / 5.0V tolerant) |
| Programming Interface | — | IEEE Std. 1149.1 JTAG (ISP) |