EPM7128AETI100-7N vs EPM7256AETI100-7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128AETI100-7N sa pamamagitan ng Altera at EPM7256AETI100-7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM7128AETI100-7N - MAX 7000A CPLD 128 Macro 84 I/O | Intel/Altera
EPM7128AETI100-7N ObsoleteIntel
EPM7256AETI100-7N - 256-MacroCell MAX 7000A CPLD, 100TQFP | Intel
EPM7256AETI100-7N ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EPM7128AETI100-7N | EPM7256AETI100-7N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Series | MAX 7000A | — |
| Family | MAX 7000A CPLD | MAX 7000A |
| Macro Cells | 128 | — |
| Number of Usable Gates | 2,500 | — |
| Number of I/O | 84 | — |
| Number of Logic Array Blocks (LABs) | 8 | — |
| Propagation Delay (tPD max) | 7 ns | — |
| Maximum Operating Frequency (fCNT) | 129.9 MHz | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V | — |
| I/O Bank Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (multi-volt I/O) | — |
| Process Technology | CMOS EEPROM | — |
| Packhaging | 100-pin TQFP (14x14 mm) | 100-pin TQFP (TQ100, 14x14 mm, 0.5 mm pitch) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | -40C to +85C (Industrial) | -40C to +85C (Industrial) |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | — |
| Tindminan RoHS | Compliant | Compliant |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Macrocells | — | 256 |
| Usable Gates | — | 5,000 |
| Maximum User I/O | — | 84 |
| Logic Elements / Blocks | — | 16 Logic Array Blocks |
| Maximum Operating Frequency | — | 126.6 MHz |
| Propagation Delay (tPD) | — | 7.5 ns |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V |
| Technology | — | CMOS, EEPROM-based configuration |
| Programmability | — | In-system programmable via JTAG (IEEE 1149.1) |
| Level ng MSL | — | 3 (168 hours) |