EPM7128ATC100-10 vs EPM7128BTC100-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128ATC100-10 sa pamamagitan ng Altera at EPM7128BTC100-10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM7128ATC100-10 - MAX 7000A CPLD, 128 Macrocells, 10ns TQFP-100 | Altera
EPM7128ATC100-10 ObsoleteIntel
EPM7128BTC100-10 - MAX 7000B CPLD, 128 Macrocells, 10ns | Intel
EPM7128BTC100-10 ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EPM7128ATC100-10 | EPM7128BTC100-10 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 7000A | MAX 7000B |
| Architecture | Multiple Array MatriX (MAX) | — |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 4 | 8 (16 macrocells each) |
| Usable Gates | 2.5K | 2.5K |
| User I/O Pins | 68 | — |
| Pin-to-Pin Logic Delay | 4.5 ns | — |
| Counter Frequency (max) | 227.3 MHz | — |
| Speed Grade | -10 (10 ns) | — |
| Core Supply Voltage | 3.3 V | — |
| I/O Logic Level Support | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| Program Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Packhaging | 100-pin TQFP (TC100) | TQFP-100 |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | Compliant (lead-free) |
| User I/Os | — | 84 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Frequency (fCNT) | — | 125 MHz |
| Core Voltage (VCCINT) | — | 2.5 V |
| I/O Voltage (VCCIO) | — | 3.3 V (5V tolerant inputs) |
| Programming Interface | — | JTAG (IEEE 1149.1) / ISP |
| Technology | — | CMOS EEPROM |