EPM7128ELC84-10 vs EPM7128ELC84-12 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128ELC84-10 sa pamamagitan ng Intel at EPM7128ELC84-12 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM7128ELC84-10 | EPM7128ELC84-12 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Obsolete |
| Family | MAX 7000 | MAX 7000 (MAX 7000E series) |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 128 | 128 |
| Equivalent Logic Gates | [DATA_NEEDED: equivalent gate count from datasheet] | — |
| User I/Os | 68 | 84 |
| Dedicated Inputs | 12 | — |
| Operating Voltage (VCCINT/VCClO) | 5 V | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Counter Frequency (fCNT) | [DATA_NEEDED: fCNT from datasheet] | — |
| Packhaging | 84-pin PLCC (J-Lead) | 84-pin PLCC (J-Lead, QCCJ) |
| Uri ng Pagpapasok | Surface Mount / Socket | Surface Mount (PLCC socket compatible) |
| Temperature na Operasyon | 0C to +70C (Commercial) | 0C to +70C (commercial) |
| Technology | EEPROM-based CMOS | — |
| Programming Interface | IEEE 1149.1 (JTAG) ISP | JTAG (IEEE 1149.1) / ISP |
| In-System Programmable | Yes | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status from datasheet] | Non-compliant (legacy 5V part, SnPb finish) |
| Lead-Free | [DATA_NEEDED: lead-free status from datasheet] | — |
| Logic Family | — | CMOS, EEPROM-based |
| Usable Gates | — | 2,500 |
| Logic Array Blocks (LABs) | — | 8 |
| Propagation Delay (tpd1) | — | 12 ns |
| Internal Global Clock Frequency | — | 90.9 MHz |
| Setup Time | — | 4.5 ns |
| Supply Voltage (VCCINT / VCCIO) | — | 5 V (4.75 V to 5.25 V) |
| Bilang ng Pin | — | 84 |