EPM7128SLC84-10 vs EPM7128SLC84-6N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128SLC84-10 sa pamamagitan ng Intel at EPM7128SLC84-6N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM7128SLC84-6N - MAX 7000S CPLD, 128 Macro, 6ns, 84-PLCC | Intel
EPM7128SLC84-6N ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EPM7128SLC84-10 | EPM7128SLC84-6N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 128 | — |
| Logic Gates | 2500 | — |
| User I/Os | 68 | — |
| Total Package Pins | 84 | — |
| Packhaging | PLCC-84 (J-lead) | 84-pin PLCC (J-lead) |
| Propagation Delay (tpd) | 10 ns | — |
| Maximum Operating Frequency | 125 MHz | 147.1 MHz |
| Internal Frequency | 250 MHz | — |
| Supply Voltage (VCCINT) | 5 V | — |
| MultiVolt I/O Support | 2.5 V / 3.3 V / 5 V | — |
| Program Memory Type | EEPROM (in-system programmable) | EEPROM |
| JTAG (IEEE 1149.1) | Yes | — |
| Temperature na Operasyon | 0C to +70C (Commercial) | [DATA_NEEDED: operating temperature range] |
| Uri ng Pagpapasok | Surface Mount (J-bend) | — |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | Non-compliant (contains lead in PLCC) | Non-Compliant (legacy 5V part) |
| Device System Gates | — | 2500 |
| Number of Macro Cells | — | 128 |
| Number of User I/Os | — | 68 |
| Number of Logic Blocks/Elements | — | 8 |
| Number of Global Clocks | — | 2 |
| Product Terms per Macro Cell | — | 32 |
| Pin-to-Pin Delay (Speed Grade) | — | 6 ns |
| Volte ng Pagbibigay | — | 5 V |
| Process Technology | — | CMOS, EEPROM |
| In-System Programmability | — | Yes (ISP via JTAG) |