EPM7128SLC84-15 vs EPM7128SLI84-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128SLC84-15 sa pamamagitan ng Intel at EPM7128SLI84-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM7128SLC84-15 - 128-Macrocell MAX 7000S CPLD, 84-PLCC | Intel / Altera
EPM7128SLC84-15 ⚠ Huling PagbiliAltera
EPM7128SLI84-10N - MAX 7000S CPLD 128 Macro 10ns 84-PLCC | Intel / Altera
EPM7128SLI84-10N NrndPagsanggunian na paghahambing
| Parametro | EPM7128SLC84-15 | EPM7128SLI84-10N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | NRND |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Macrocells | 128 | — |
| Usable Gates | 2,500 | 2,500 |
| User I/Os | 68 (in 84-PLCC) | 68 |
| Packhaging | 84-Pin PLCC (J-Lead, J84) | 84-pin PLCC (J-Lead) |
| Speed Grade | -15 (15 ns pin-to-pin delay) | — |
| Propagation Delay (tPD) | 15 ns | 10 ns |
| Maximum Internal Frequency (fMAX) | 76.9 MHz | — |
| Logic Family / Process | CMOS, 5V, EEPROM | — |
| Supply Voltage (VCCINT) | 5 V | 4.75 V to 5.25 V (5 V typical) |
| I/O Standard Support | 5.0 V TTL/CMOS (multi-volt I/O compatible with 3.3V) | — |
| Programming Interface | JTAG (IEEE Std. 1149.1), in-system programmable | — |
| Configuration Memory | Non-volatile EEPROM (instant-on, no boot PROM) | — |
| Temperature na Operasyon | 0C to +70C (commercial) | -40 C to +85 C (Industrial) |
| Tindminan RoHS | Non-RoHS (legacy 5V part) | [DATA_NEEDED: RoHS compliance per latest Intel/Altera declaration] |
| Uri ng Pagpapasok | Surface Mount / Socketed (PLCC-84 socket) | Surface Mount |
| Logic Cells / Macro Cells | — | 128 macro cells |
| Number of Logic Elements / Blocks | — | 16 Logic Array Blocks (LABs) |
| Maximum Frequency (fMAX) | — | 125 MHz |
| I/O Voltage Tolerance | — | 3.3 V / 5 V MultiVolt I/O |
| Process Technology | — | CMOS EEPROM |
| Programmability | — | In-system programmable (ISP), non-volatile EEPROM |
| Boundary-Scan (JTAG) | — | IEEE Std 1149.1 compliant |
| Lead-Free | — | [DATA_NEEDED: lead-free per latest Intel/Altera declaration] |