EPM7128SQC100-10 vs EPM7128STC100-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128SQC100-10 sa pamamagitan ng Altera at EPM7128STC100-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM7128STC100-10 - 128-Macro MAX 7000S CPLD, 10ns TQFP-100 | Intel / Altera
EPM7128STC100-10 ObsoletePagsanggunian na paghahambing
| Parametro | EPM7128SQC100-10 | EPM7128STC100-10 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 | 128 |
| Logic Elements / Gates | 2,500 usable gates | — |
| Maximum User I/O | 84 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum Operating Frequency | 100 MHz | — |
| Pin-to-Pin Logic Delay (tPD) | 10 ns | — |
| Volte ng Pagbibigay | 5 V | — |
| Process Technology | 5V CMOS, EEPROM-based | — |
| Programmability | In-System Programmable (ISP) via JTAG | In-System Programmable (JTAG, IEEE 1149.1), EEPROM |
| Packhaging | 100-pin PQFP (Plastic Quad Flat Pack) | TQFP-100 (C100) |
| Temperature na Operasyon | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS compliance status not in provided data] |
| Usable Gates | — | 2,500 |
| User I/Os | — | 84 |
| Logic Array Blocks | — | 8 (16 macrocells per LAB) |
| Propagation Delay (tPD) | — | 10 ns |
| Internal Counter Frequency (fCNT) | — | 100 MHz |
| Logic Family | — | CMOS |
| Supply Voltage (VCCINT) | — | 5 V |
| MultiVolt I/O Voltage | — | 3.3 V / 5 V |
| Bilang ng Pin | — | 100 |