EPM7128SQI100-10 vs EPM7128SQC100-7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128SQI100-10 sa pamamagitan ng Altera at EPM7128SQC100-7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM7128SQI100-10 - MAX 7000S CPLD 128-Macrocell 84-IO 10ns | Altera
EPM7128SQI100-10 ObsoleteIntel
EPM7128SQC100-7N - MAX 7000 CPLD, 128 Macrocells, 7.5ns, 100-Pin PQFP | Intel (Altera)
EPM7128SQC100-7N ObsoletePagsanggunian na paghahambing
| Parametro | EPM7128SQI100-10 | EPM7128SQC100-7N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD - Complex Programmable Logic Device |
| Macro Cells | 128 | — |
| User I/Os | 84 | — |
| Usable Gates | 2,500 | 2,500 |
| Logic Blocks (LABs) | 8 (16 macrocells each) | — |
| Package Type | PQFP-100 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | 7.5 ns |
| Maximum Internal Frequency | 125 MHz to 250 MHz | — |
| Counter Speed | Up to 175.4 MHz | 175.4 MHz |
| Operating Voltage (VCC) | 5 V | — |
| Temperature na Operasyon | -40C to +85C (Industrial) | 0C to +70C (commercial) |
| Configuration Memory | EEPROM (non-volatile) | — |
| Program/Erase Cycles | 100 minimum | — |
| In-System Programming | Yes (JTAG IEEE 1149.1) | — |
| Logic Family | CMOS | — |
| I/O Compatibility | TTL-compatible, 5V/3.3V multi-voltage | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status not in provided data] | Compliant (lead-free 'N' suffix) |
| Program Memory Type | — | EEPROM |
| Number of Macrocells | — | 128 |
| Number of Logic Array Blocks | — | 8 |
| Number of Global Clocks | — | 2 |
| Product Terms per Macrocell | — | 32 |
| System Gates | — | 5,000 (max) |
| Maximum User I/Os | — | 84 |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Operating Voltage (Core) | — | 5.0 V |
| I/O Standard Support | — | multiVolt (2.5V, 3.3V, 5.0V) |
| Packhaging | — | 100-pin PQFP (QFP-100) |
| Process Technology | — | 0.30 µm CMOS EEPROM |
| Security Bit | — | Programmable (one per device) |