EPM7128STC100-7 vs EPM7128STC100-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128STC100-7 sa pamamagitan ng Intel at EPM7128STC100-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM7128STC100-10 - 128-Macro MAX 7000S CPLD, 10ns TQFP-100 | Intel / Altera
EPM7128STC100-10 ObsoletePagsanggunian na paghahambing
| Parametro | EPM7128STC100-7 | EPM7128STC100-10 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | MAX 7000S | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 | 128 |
| Usable Gates | 2,500 | 2,500 |
| Logic Array Blocks (LABs) | 8 | — |
| User I/Os | 84 | 84 |
| Propagation Delay (tPD) | 7.5 ns | 10 ns |
| Internal Frequency | 125 MHz | — |
| Supply Voltage (VCCINT) | 5 V | 5 V |
| Logic Family | CMOS | CMOS |
| Programmable Pin Count | 100 | — |
| Packhaging | 100-Pin TQFP (TQFP-100) | TQFP-100 (C100) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0C to +70C (Commercial) | 0C to +70C (commercial) |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS compliance status not in provided data] |
| Family | — | MAX 7000S |
| Logic Array Blocks | — | 8 (16 macrocells per LAB) |
| Internal Counter Frequency (fCNT) | — | 100 MHz |
| MultiVolt I/O Voltage | — | 3.3 V / 5 V |
| Bilang ng Pin | — | 100 |
| Programmability | — | In-System Programmable (JTAG, IEEE 1149.1), EEPROM |