EPM7128STC100-7 vs EPM7128STC100-10 比較
詳細並排比較 EPM7128STC100-7 由 Intel 與 EPM7128STC100-10 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM7128STC100-10 - 128-Macro MAX 7000S CPLD, 10ns TQFP-100 | Intel / Altera
EPM7128STC100-10 Obsolete規格比較
| 參數 | EPM7128STC100-7 | EPM7128STC100-10 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Series | MAX 7000S | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 | 128 |
| Usable Gates | 2,500 | 2,500 |
| Logic Array Blocks (LABs) | 8 | — |
| User I/Os | 84 | 84 |
| Propagation Delay (tPD) | 7.5 ns | 10 ns |
| Internal Frequency | 125 MHz | — |
| Supply Voltage (VCCINT) | 5 V | 5 V |
| Logic Family | CMOS | CMOS |
| Programmable Pin Count | 100 | — |
| 封裝 | 100-Pin TQFP (TQFP-100) | TQFP-100 (C100) |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | 0C to +70C (Commercial) | 0C to +70C (commercial) |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| RoHS 狀態 | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS compliance status not in provided data] |
| Family | — | MAX 7000S |
| Logic Array Blocks | — | 8 (16 macrocells per LAB) |
| Internal Counter Frequency (fCNT) | — | 100 MHz |
| MultiVolt I/O Voltage | — | 3.3 V / 5 V |
| 腳位數 | — | 100 |
| Programmability | — | In-System Programmable (JTAG, IEEE 1149.1), EEPROM |