EPM7128STC100-7 vs EPM7128STC100-6N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128STC100-7 sa pamamagitan ng Intel at EPM7128STC100-6N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM7128STC100-6N - MAX 7000S 128-Macro-Cell CPLD | Altera | TQFP-100
EPM7128STC100-6N ObsoletePagsanggunian na paghahambing
| Parametro | EPM7128STC100-7 | EPM7128STC100-6N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | MAX 7000S | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 128 | 128 |
| Usable Gates | 2,500 | 2,500 |
| Logic Array Blocks (LABs) | 8 | — |
| User I/Os | 84 | 84 |
| Propagation Delay (tPD) | 7.5 ns | 6 ns |
| Internal Frequency | 125 MHz | — |
| Supply Voltage (VCCINT) | 5 V | — |
| Logic Family | CMOS | CMOS |
| Programmable Pin Count | 100 | — |
| Packhaging | 100-Pin TQFP (TQFP-100) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | Non-Compliant (lead-bearing package) |
| Family | — | MAX 7000S |
| Bilang ng Pins | — | 100 |
| Package Type | — | TQFP-100 |
| Maximum Internal Frequency | — | 147.1 MHz |
| Internal Counter Frequency | — | 250 MHz |
| Pin-to-Pin Delay | — | 4.5 ns |
| Supply Voltage (VCCIO) | — | 5 V |
| Process Technology | — | CMOS EEPROM |
| Programmability | — | In-System Programmable (ISP) via JTAG |
| JTAG Support | — | IEEE 1149.1 Boundary Scan |