EPM7128STI100-10N vs EPM7128STC100-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128STI100-10N sa pamamagitan ng Altera at EPM7128STC100-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM7128STI100-10N - 128-Macrocell CPLD, 10ns, 100-pin TQFP | Altera
EPM7128STI100-10N ObsoleteAltera
EPM7128STC100-10N - MAX 7000S CPLD 128-Macrocell 10ns TQFP-100 | Altera
EPM7128STC100-10N NrndPagsanggunian na paghahambing
| Parametro | EPM7128STI100-10N | EPM7128STC100-10N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 7000S | MAX 7000S |
| Architecture | CMOS EEPROM-based CPLD | — |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 (up to 5,000 family max) | 2,500 |
| Logic Array Blocks (LABs) | 8 | 8 (16 macrocells each) |
| Maximum User I/O | 84 | — |
| Pin-to-Pin Logic Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 175.4 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | Yes (IEEE 1149.1 JTAG) |
| JTAG Boundary-Scan | Yes (BST) | — |
| Packhaging | 100-pin TQFP | 100-pin TQFP (14 x 14 x 1 mm) |
| Temperature na Operasyon | -40C to +85C (Industrial) | 0 C to +70 C (commercial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant (Pb-free "N" suffix) |
| Open-Drain I/O Option | Available (per MAX 7000A feature set) | — |
| Product Type | — | CPLD - Complex Programmable Logic Device |
| User I/Os | — | 84 |
| Propagation Delay (tPD) | — | 10 ns |
| Internal Frequency (fMAX) | — | 100 MHz |
| Supply Voltage (VCCINT) | — | 5 V |
| I/O Voltage (VCCIO) | — | 3.3 V or 5 V (MultiVolt) |
| Process Technology | — | CMOS EEPROM |
| Lead-Free | — | Yes |