EPM7160SQC160-7 vs EPM7160SQC160-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7160SQC160-7 sa pamamagitan ng Altera at EPM7160SQC160-10N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM7160SQC160-7 | EPM7160SQC160-10N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 7000S | MAX 7000S |
| Macrocells | 160 | — |
| Logic Array Blocks (LABs) | 10 | — |
| Usable System Gates | 3,200 | — |
| Product Terms per Macrocell | 32 | — |
| Maximum User I/Os | 104 | — |
| Global Clocks | 2 | — |
| Speed Grade | -7 (7.5 ns pin-to-pin) | — |
| Maximum Propagation Delay (tPD) | 7.5 ns | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) | 5.0 V |
| Program Memory Type | EEPROM (in-system programmable) | — |
| Temperature na Operasyon | 0 °C to 70 °C (commercial) | 0 C to 70 C (Commercial) |
| Packhaging | 160-pin PQFP (BQFP, 28x28 mm) | PQFP-160 (SQC) 31.2 x 31.2 mm |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| JTAG (IEEE 1149.1) | Yes (ISP via JTAG) | — |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 | — |
| Tindminan RoHS | Not Compliant (per Arrow listing) | Non-Compliant (Pb-bearing PQFP) |
| Part Status | Obsolete | — |
| Macro Cells | — | 160 |
| Usable Gates | — | 3,200 |
| Logic Elements / Blocks | — | 10 Logic Array Blocks (LABs) |
| User I/O Pins | — | 104 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Internal Frequency | — | 167 MHz |
| Counter Speed (fCNT) | — | 100 MHz |
| In-System Programmability | — | Yes (JTAG IEEE 1149.1) |
| Memory Technology | — | EEPROM |