EPM7160SQC160-7 vs EPM7160SQC160-6 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7160SQC160-7 sa pamamagitan ng Altera at EPM7160SQC160-6 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM7160SQC160-6 - 160-Macrocell MAX 7000S CPLD, 6ns, PQFP-160 | Altera
EPM7160SQC160-6 ObsoletePagsanggunian na paghahambing
| Parametro | EPM7160SQC160-7 | EPM7160SQC160-6 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 7000S | — |
| Macrocells | 160 | — |
| Logic Array Blocks (LABs) | 10 | — |
| Usable System Gates | 3,200 | — |
| Product Terms per Macrocell | 32 | — |
| Maximum User I/Os | 104 | — |
| Global Clocks | 2 | — |
| Speed Grade | -7 (7.5 ns pin-to-pin) | — |
| Maximum Propagation Delay (tPD) | 7.5 ns | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) | 4.75 V to 5.25 V (nominal 5 V) |
| Program Memory Type | EEPROM (in-system programmable) | — |
| Temperature na Operasyon | 0 °C to 70 °C (commercial) | 0 C to 70 C (commercial) |
| Packhaging | 160-pin PQFP (BQFP, 28x28 mm) | 160-pin PQFP (Plastic Quad Flat Pack), 28x28 mm body |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| JTAG (IEEE 1149.1) | Yes (ISP via JTAG) | — |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 | — |
| Tindminan RoHS | Not Compliant (per Arrow listing) | — |
| Part Status | Obsolete | — |
| Series | — | MAX 7000S |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Programmable Type | — | In System Programmable (ISP), EEPROM-based |
| Number of Macrocells | — | 160 |
| Number of Logic Elements/Blocks | — | 10 LABs (Logic Array Blocks) |
| Number of Usable Gates | — | 3,200 |
| Number of I/O Pins | — | 104 |
| Propagation Delay (tpd) | — | 6 ns (max, pin-to-pin) |
| Maximum Internal Frequency | — | 167 MHz |
| Logic Family | — | CMOS, TTL-compatible I/O |
| Program/Erase Endurance | — | 100 cycles (EEPROM) |
| JTAG / Boundary Scan | — | IEEE Std 1149.1 compliant |
| Dedicated Input Pins | — | 4 (GCLK1, GCLRn, OE1, OE2/GCLK2) |