EPM7160SQC160-7 vs EPM7160SQC160-6 比較
詳細並排比較 EPM7160SQC160-7 由 Altera 與 EPM7160SQC160-6 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM7160SQC160-6 - 160-Macrocell MAX 7000S CPLD, 6ns, PQFP-160 | Altera
EPM7160SQC160-6 Obsolete規格比較
| 參數 | EPM7160SQC160-7 | EPM7160SQC160-6 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 7000S | — |
| Macrocells | 160 | — |
| Logic Array Blocks (LABs) | 10 | — |
| Usable System Gates | 3,200 | — |
| Product Terms per Macrocell | 32 | — |
| Maximum User I/Os | 104 | — |
| Global Clocks | 2 | — |
| Speed Grade | -7 (7.5 ns pin-to-pin) | — |
| Maximum Propagation Delay (tPD) | 7.5 ns | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) | 4.75 V to 5.25 V (nominal 5 V) |
| Program Memory Type | EEPROM (in-system programmable) | — |
| 工作溫度 | 0 °C to 70 °C (commercial) | 0 C to 70 C (commercial) |
| 封裝 | 160-pin PQFP (BQFP, 28x28 mm) | 160-pin PQFP (Plastic Quad Flat Pack), 28x28 mm body |
| 安裝類型 | Surface Mount | Surface Mount |
| JTAG (IEEE 1149.1) | Yes (ISP via JTAG) | — |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 | — |
| RoHS 狀態 | Not Compliant (per Arrow listing) | — |
| Part Status | Obsolete | — |
| Series | — | MAX 7000S |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Programmable Type | — | In System Programmable (ISP), EEPROM-based |
| Number of Macrocells | — | 160 |
| Number of Logic Elements/Blocks | — | 10 LABs (Logic Array Blocks) |
| Number of Usable Gates | — | 3,200 |
| Number of I/O Pins | — | 104 |
| Propagation Delay (tpd) | — | 6 ns (max, pin-to-pin) |
| Maximum Internal Frequency | — | 167 MHz |
| Logic Family | — | CMOS, TTL-compatible I/O |
| Program/Erase Endurance | — | 100 cycles (EEPROM) |
| JTAG / Boundary Scan | — | IEEE Std 1149.1 compliant |
| Dedicated Input Pins | — | 4 (GCLK1, GCLRn, OE1, OE2/GCLK2) |