EPM7160STC100-10 vs EPM7160STC100-10N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM7160STC100-10 sa pamamagitan ng Intel at EPM7160STC100-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM7160STC100-10 EPM7160STC100-10N
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili Obsolete
Family MAX 7000S MAX 7000S
Device Type CPLD (Complex Programmable Logic Device) —
Macro Cells 160 —
User I/Os 84 84
Usable Gates 3,200 —
Logic Elements 160 macrocells / 10 Logic Array Blocks —
Supply Voltage (VCC) 5.0 V (4.75 V - 5.25 V) —
Propagation Delay (tPD1) 10 ns —
Global Clock Setup Time 6 ns —
Internal Counter Frequency 100 MHz —
Technology CMOS, EEPROM-based —
In-System Programmability Yes (IEEE 1149.1 JTAG) —
Packhaging 100-pin TQFP TQFP-100 (1 mm height, plastic)
Temperature na Operasyon 0 C to +70 C (commercial) 0C to +70C (Commercial)
Uri ng Pagpapasok Surface Mount Surface Mount
Tindminan RoHS Non-RoHS (legacy Altera part; -10N variant is RoHS) [DATA_NEEDED: RoHS status]
Macrocells — 160
Equivalent Gates — 3.2K
Propagation Delay (tPD) — 10 ns
Internal Operating Frequency — 167 MHz max
Supply Voltage (VCCINT) — 4.75 V to 5.25 V
I/O Voltage (VCCIO) — 3.0 V to 5.25 V (MultiVolt)
Logic Family — CMOS
Programmable Type — In-System Programmable (ISP) via JTAG
Configuration Memory — EEPROM (non-volatile)
JTAG (IEEE 1149.1) — Yes
PCI Compliance — Yes (66 MHz)
Level ng MSL — [DATA_NEEDED: MSL level]

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