EPM7160STC100-10N vs EPM7160STI100-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM7160STC100-10N sa pamamagitan ng Altera at EPM7160STI100-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM7160STC100-10N EPM7160STI100-10
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 7000S MAX 7000S
Macrocells 160 160
User I/Os 84 84
Equivalent Gates 3.2K —
Propagation Delay (tPD) 10 ns 10 ns
Internal Operating Frequency 167 MHz max —
Supply Voltage (VCCINT) 4.75 V to 5.25 V —
I/O Voltage (VCCIO) 3.0 V to 5.25 V (MultiVolt) —
Logic Family CMOS —
Programmable Type In-System Programmable (ISP) via JTAG In-System Programmable (EEPROM)
Configuration Memory EEPROM (non-volatile) —
Packhaging TQFP-100 (1 mm height, plastic) TQFP-100 (100-pin Thin Quad Flat Pack)
Temperature na Operasyon 0C to +70C (Commercial) -40 C to +85 C (Industrial)
Uri ng Pagpapasok Surface Mount Surface Mount
JTAG (IEEE 1149.1) Yes —
PCI Compliance Yes (66 MHz) PCI Local Bus Specification Rev. 2.2 (for -10 speed grade)
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status - not explicitly stated in provided data]
Level ng MSL [DATA_NEEDED: MSL level] [DATA_NEEDED: MSL rating]
Usable Gates — 3,200
Logic Elements / Blocks — 16 Logic Array Blocks (LABs)
Maximum Operating Frequency — 100 MHz
Internal Supply Voltage — 4.75 V to 5.25 V
I/O Supply Voltage — 5.0 V
JTAG / Boundary Scan — IEEE Std. 1149.1 compliant
Lead-Free — [DATA_NEEDED: lead-free status]

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