EPM7256AQC208-7 vs EPM7256SQC208-15 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM7256AQC208-7 sa pamamagitan ng Altera at EPM7256SQC208-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM7256AQC208-7 EPM7256SQC208-15
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND NRND
Family MAX 7000A MAX 7000S
Programmable Type In System Programmable (ISP), EEPROM-based —
Macrocells 256 256
Usable Gates 5,000 5000
Logic Array Blocks (LABs) 16 16
Maximum User I/O Pins 164 —
Pin-to-Pin Logic Delay (tPD) 7 ns —
Maximum Counter Frequency 125 MHz —
Internal Toggle Frequency 227.3 MHz —
Supply Voltage - Internal 3.0 V to 3.6 V —
I/O Voltage Compatibility 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) —
Packhaging 208-Pin PQFP (28 x 28 mm) 208-pin PQFP (28x28 mm)
Supplier Device Package 208-PQFP (28x28) —
Uri ng Pagpapasok Surface Mount Surface Mount
Hanay ng Temperature na Operasyon 0C to +70C (commercial) 0 C to +70 C (Commercial)
JTAG Interface IEEE 1149.1 (JTAG) boundary scan —
Configuration Memory EEPROM (non-volatile) EEPROM (non-volatile)
Speed Grade -7 —
Tindminan RoHS [DATA_NEEDED: RoHS status] Contains lead / RoHS non-compliant (per third-party listing)
Level ng MSL [DATA_NEEDED: MSL level] —
Series — EPM7256
Device Type — CPLD (Complex Programmable Logic Device)
User I/O Pins — 164
Pin-to-Pin Delay (tPD) — 15 ns
Supply Voltage (VCCINT) — 4.75 V to 5.25 V
Programmable Power Mode — Yes (per-macrocell turbo-bit)
JTAG (IEEE 1149.1) Boundary-Scan — Yes
In-System Programmability (ISP) — Yes
Lead-Free Status — Contains lead

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