EPM9320ALC84-10 vs EPM9320LC84-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320ALC84-10 sa pamamagitan ng Intel at EPM9320LC84-15 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9320ALC84-10 | EPM9320LC84-15 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device | EPM9320 | — |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 16 | 20 |
| Maximum User I/O Pins | 52 | — |
| Dedicated Inputs | 16 | — |
| Speed Grade | -10 (10 ns pin-to-pin delay) | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| In-System Programmability | 5.0 V ISP via IEEE 1149.1 JTAG | — |
| Technology | CMOS EEPROM-based, third-generation MAX | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) |
| PCI Compliance | PCI Local Bus Specification Rev. 2.2 (speed grade -10) | — |
| Packhaging | 84-pin PLCC (J-Lead) | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Temperature na Operasyon | [DATA_NEEDED: commercial/industrial grade] | -40C to +85C (commercial) [DATA_NEEDED: exact grade] |
| Uri ng Pagpapasok | Surface Mount / Through-Hole (PLCC socket) | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED] | [DATA_NEEDED: confirm from manufacturer] |
| Non-Volatile Configuration | Yes (EEPROM cell, powers up in known state) | — |
| Architecture | MAX (Multiple Array MatriX) with FastTrack Interconnect | — |
| Series | — | EPM9320 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 6,000 |
| Propagation Delay (tPD) | — | 15 ns (max) |
| Maksimum na Taktiko ng Oras | — | 117.6 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5.0 V nominal) |
| Programmability | — | 5.0 V in-system programmable (ISP) via JTAG |
| JTAG Interface | — | IEEE Std. 1149.1 boundary-scan compliant |
| Built-in Pull-up Resistors | — | Yes, on every I/O pin |
| Architecture Feature | — | Pin-locking across design iterations |