EPM9320ALC84-10 vs EPM9320LC84-15 对比

详细并排对比 EPM9320ALC84-10 出自 Intel 和 EPM9320LC84-15 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9320ALC84-10 EPM9320LC84-15
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $19.80 $17.95
Family MAX 9000 MAX 9000
Device EPM9320 —
Macrocells 320 320
Logic Array Blocks (LABs) 16 20
Maximum User I/O Pins 52 —
Dedicated Inputs 16 —
Speed Grade -10 (10 ns pin-to-pin delay) —
Pin-to-Pin Delay (tPD) 10 ns —
Supply Voltage (VCCINT) 5.0 V —
In-System Programmability 5.0 V ISP via IEEE 1149.1 JTAG —
Technology CMOS EEPROM-based, third-generation MAX CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX)
PCI Compliance PCI Local Bus Specification Rev. 2.2 (speed grade -10) —
封装 84-pin PLCC (J-Lead) 84-pin PLCC (Plastic Leaded Chip Carrier)
工作温度 [DATA_NEEDED: commercial/industrial grade] -40C to +85C (commercial) [DATA_NEEDED: exact grade]
安装类型 Surface Mount / Through-Hole (PLCC socket) Surface Mount
RoHS 状态 [DATA_NEEDED] [DATA_NEEDED: confirm from manufacturer]
Non-Volatile Configuration Yes (EEPROM cell, powers up in known state) —
Architecture MAX (Multiple Array MatriX) with FastTrack Interconnect —
Series — EPM9320
Device Type — CPLD (Complex Programmable Logic Device)
Usable Gates — 6,000
Propagation Delay (tPD) — 15 ns (max)
最大时钟频率 — 117.6 MHz
Supply Voltage (VCC) — 4.75 V to 5.25 V (5.0 V nominal)
Programmability — 5.0 V in-system programmable (ISP) via JTAG
JTAG Interface — IEEE Std. 1149.1 boundary-scan compliant
Built-in Pull-up Resistors — Yes, on every I/O pin
Architecture Feature — Pin-locking across design iterations

数据手册与资源

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