EPM9320ALI84-10 vs EPM9320ALC84-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320ALI84-10 sa pamamagitan ng Intel at EPM9320ALC84-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9320ALI84-10 | EPM9320ALC84-15 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Family | MAX 9000 | MAX 9000 CPLD |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 6,000 to 12,000 | 6000 |
| Macrocells | 320 | 320 |
| User I/O Pins | 84 | — |
| Packhaging | 84-pin PLCC (Plastic Leaded Chip Carrier) | 84-pin PLCC (S-PQCC-J84, J-lead) |
| Pin-to-Pin Delay (Tpd1) | 10 ns | — |
| Maximum Counter Frequency | 144 MHz | — |
| Supply Voltage (VCC) | 5.0 V | 4.75 V to 5.25 V (5 V nominal) |
| In-System Programmability | Yes, via IEEE 1149.1 JTAG | — |
| Program Memory Technology | CMOS EEPROM | — |
| Process Technology | CMOS | — |
| Architecture | Multiple Array MatriX (MAX) | — |
| Hanay ng Temperature na Operasyon | -40C to +85C (Industrial) | — |
| Uri ng Pagpapasok | Surface Mount (PLCC socket compatible) | Through-hole / socket |
| Propagation Delay (tPD) | — | 16 ns |
| User I/O | — | 56 |
| Logic Array Blocks (LABs) | — | 16 |
| Technology | — | CMOS, EEPROM-based configuration |
| Programming Interface | — | JTAG (IEEE 1149.1) / ISP |
| Temperature na Operasyon | — | -40C to +85C (industrial) |
| Tindminan RoHS | — | [DATA_NEEDED: rohs status] |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | — | MSL-3 (168 hours per fpgalink.com) |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED: lead free status] |
| RoHS3 Compliance | — | ROHS3 Compliant (per fpgalink.com listing) |