EPM9320ALI84-10 vs EPM9320ALC84-15 Comparison
Detailed side-by-side comparison of EPM9320ALI84-10 by Intel and EPM9320ALC84-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320ALI84-10 | EPM9320ALC84-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | NRND |
| Family | MAX 9000 | MAX 9000 CPLD |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 6,000 to 12,000 | 6000 |
| Macrocells | 320 | 320 |
| User I/O Pins | 84 | — |
| Package | 84-pin PLCC (Plastic Leaded Chip Carrier) | 84-pin PLCC (S-PQCC-J84, J-lead) |
| Pin-to-Pin Delay (Tpd1) | 10 ns | — |
| Maximum Counter Frequency | 144 MHz | — |
| Supply Voltage (VCC) | 5.0 V | 4.75 V to 5.25 V (5 V nominal) |
| In-System Programmability | Yes, via IEEE 1149.1 JTAG | — |
| Program Memory Technology | CMOS EEPROM | — |
| Process Technology | CMOS | — |
| Architecture | Multiple Array MatriX (MAX) | — |
| Operating Temperature Range | -40C to +85C (Industrial) | — |
| Mounting Type | Surface Mount (PLCC socket compatible) | Through-hole / socket |
| Propagation Delay (tPD) | — | 16 ns |
| User I/O | — | 56 |
| Logic Array Blocks (LABs) | — | 16 |
| Technology | — | CMOS, EEPROM-based configuration |
| Programming Interface | — | JTAG (IEEE 1149.1) / ISP |
| Operating Temperature | — | -40C to +85C (industrial) |
| RoHS Status | — | [DATA_NEEDED: rohs status] |
| Moisture Sensitivity Level (MSL) | — | MSL-3 (168 hours per fpgalink.com) |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED: lead free status] |
| RoHS3 Compliance | — | ROHS3 Compliant (per fpgalink.com listing) |