EPM9320LC84-10 vs EPM9320ALI84-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320LC84-10 sa pamamagitan ng Intel at EPM9320ALI84-10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9320LC84-10 EPM9320ALI84-10
Brand Intel Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND NRND
Family MAX 9000 EPLD MAX 9000
Device EPM9320 —
Macrocells 320 320
Usable Gates 6000 (typical) 6,000 to 12,000
Logic Array Blocks (LABs) 16 —
Maximum User I/O Pins 168 (varies by package) —
Pin-to-Pin Logic Delay (tPD) 10 ns —
Maximum Frequency (fCNT) [DATA_NEEDED: fCNT in MHz] —
Supply Voltage (VCC) 5.0 V (typical, see datasheet) 5.0 V
Process Technology 0.7 µm CMOS EEPROM/UV-EPROM CMOS
Packhaging 84-pin PLCC (JEDEC MO-047) 84-pin PLCC (Plastic Leaded Chip Carrier)
Uri ng Pagpapasok Surface Mount (PLCC socket also common) Surface Mount (PLCC socket compatible)
Temperature na Operasyon 0C to +70C (commercial) [DATA_NEEDED: exact grade suffix] —
Programming Interface JTAG (IEEE 1149.1) boundary-scan, Altera ByteBlaster compatible —
Configuration Non-volatile EEPROM (instant-on, no boot PROM) —
Tindminan RoHS ROHS3 Compliant (per fpgalink listing) —
Level ng Sensitivity sa Asid ng Moisture (MSL) MSL-3, 168 hours (per fpgalink listing) —
Manufacturer Lead Time 1-7 days (per fpgalink listing) —
Product Type — CPLD (Complex Programmable Logic Device)
User I/O Pins — 84
Pin-to-Pin Delay (Tpd1) — 10 ns
Maximum Counter Frequency — 144 MHz
In-System Programmability — Yes, via IEEE 1149.1 JTAG
Program Memory Technology — CMOS EEPROM
Architecture — Multiple Array MatriX (MAX)
Hanay ng Temperature na Operasyon — -40C to +85C (Industrial)

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