EPM9320LC84-20 vs EPM9320ALC84-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320LC84-20 sa pamamagitan ng Altera at EPM9320ALC84-10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9320LC84-20 | EPM9320ALC84-10 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Macrocells | 320 | 320 |
| User I/Os | 60 | — |
| Logic Family | CMOS (EEPROM-based) | — |
| Packhaging | PLCC-84 (Plastic Leaded Chip Carrier) | 84-pin PLCC (J-Lead) |
| Pins | 84 | — |
| Propagation Delay (tPD) | 16 ns | — |
| Internal Counter Frequency | 118 MHz | — |
| Volte ng Pagbibigay | 5.0 V | — |
| Temperature na Operasyon | 0 C to 70 C | [DATA_NEEDED: commercial/industrial grade] |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | 5.0 V ISP via IEEE 1149.1 JTAG |
| Dedicated Inputs | 4 (global clock / clear / OE) | 16 |
| Architecture | Multiple Array MatriX (MAX), 3rd generation | MAX (Multiple Array MatriX) with FastTrack Interconnect |
| PCI Compliance | PCI Local Bus Specification Rev. 2.2 | PCI Local Bus Specification Rev. 2.2 (speed grade -10) |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED] |
| Device | — | EPM9320 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 52 |
| Speed Grade | — | -10 (10 ns pin-to-pin delay) |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Supply Voltage (VCCINT) | — | 5.0 V |
| Technology | — | CMOS EEPROM-based, third-generation MAX |
| Uri ng Pagpapasok | — | Surface Mount / Through-Hole (PLCC socket) |
| Non-Volatile Configuration | — | Yes (EEPROM cell, powers up in known state) |