EPM9320LC84-20N vs EPM9320LI84-20N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320LC84-20N sa pamamagitan ng Intel at EPM9320LI84-20N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9320LC84-20N EPM9320LI84-20N
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Aktibo Obsolete
Series MAX 9000 —
Logic Family CMOS (EEPROM-based) CMOS, EEPROM-based
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Usable Gates 6,000 6,000 to 12,000
Macrocells 320 320
User I/Os 60 —
Bilang ng Pins 84 —
Package Type Plastic Leaded Chip Carrier (PLCC-84, J-bend) —
Package Code QCCJ —
Propagation Delay (tPD) 16 ns 20 ns (speed grade -20)
Internal Frequency 118 MHz —
Supply Voltage (VCC) 5 V —
Temperature na Operasyon 0 C to +70 C (Commercial) 0 C to +70 C (commercial)
Programming 5.0-V In-System Programmable via JTAG (IEEE 1149.1) —
Uri ng Pagpapasok Surface Mount (J-bend) —
Terminal Form J BEND —
Level ng MSL [DATA_NEEDED: MSL moisture sensitivity level] —
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance status]
Family — MAX 9000
User I/O Pins — 60
Total Pins — 84
Packhaging — PLCC-84 (Plastic Leaded Chip Carrier, J-lead)
Pin-to-Pin Delay — 16 ns (per DigChip spec block)
Maximum Counter Frequency — 118 MHz
Volte ng Pagbibigay — 5.0 V
Programming Interface — IEEE 1149.1 JTAG, in-system programmable
Architecture — Multiple Array MatriX (MAX) - third generation
Process Technology — Advanced CMOS EEPROM

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