EPM9400LC84-15 vs EPM9400LC84-20 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9400LC84-15 sa pamamagitan ng Altera at EPM9400LC84-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9400LC84-15 EPM9400LC84-20
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Usable Gates 8,000 8,000 (6,000 to 12,000 typical range)
Macro Cells 400 —
Logic Array Blocks 25 —
Maximum User I/Os 59 —
Maximum Operating Frequency 117.6 MHz —
Speed Grade -15 (15 ns pin-to-pin delay) —
Core Supply Voltage (VCCINT) 5.0 V —
Input Logic Compatibility TTL, 3.3 V and 5.0 V tolerant —
Configuration Memory EEPROM (non-volatile, in-system programmable) —
JTAG Interface IEEE Std. 1149.1 compliant (ISP) —
Packhaging 84-pin PLCC 84-pin PLCC (Plastic Leaded Chip Carrier)
Uri ng Pagpapasok Surface Mount Surface Mount (PLCC socket or SMT land pattern)
Temperature na Operasyon 0C to +70C (Commercial) Commercial (0C to +70C) - assumed from -20 speed grade
Minimum VCCINT 4.75 V —
Programming Method In-System Programmable via JTAG —
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Architecture — Multiple Array Matrix (MAX), 3rd generation, EEPROM-based
Macrocells — 400
Flip-Flops — 580
Maximum User I/O — 55
Pin-to-Pin Propagation Delay — 20 ns (speed grade -20)
Maximum Counter Frequency — 144 MHz
Supply Voltage (VCCINT) — 5 V
I/O Voltage (VCCIO) — 3.3 V or 5 V (configurable)
In-System Programming — Yes (IEEE 1149.1 JTAG)
Process Technology — CMOS EEPROM

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