EPM9560GC280-15N vs EPM9560GC280-15 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560GC280-15N sa pamamagitan ng Intel at EPM9560GC280-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9560GC280-15N EPM9560GC280-15
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Device Family MAX 9000 —
Product Type EE PLD / CPLD —
Macrocell Count 560 —
Usable Gates 12,000 (typical) —
Propagation Delay (tPD) 16.6 ns —
Maksimum na Taktiko ng Oras 117.6 MHz —
Supply Voltage (VCCINT/VCCIO) 5.0 V 5.0 V
Maximum Supply Voltage 5.25 V —
Logic Technology CMOS EEPROM —
In-System Programmability Yes (5.0-V ISP via JTAG) —
Boundary-Scan (JTAG) IEEE Std. 1149.1 compliant —
Packhaging CPGA-280 (Ceramic Pin Grid Array, 280 pins) —
Package Code PGA / CPGA280 —
Terminal Form PIN/PEG —
Operating Temperature Grade Commercial —
Architecture Multiple Array MatriX (MAX) 3rd generation Multiple Array MatriX (MAX)
Family — MAX 9000
Device Type — EE PLD (CMOS EEPROM-based CPLD)
Macro Cells — 560
Typical Gates — 12,000
Maximum Operating Frequency — 117.6 MHz
Propagation Delay (tpd) — 15 ns (speed grade -15)
Propagation Delay (alternate datasheet figure) — 16.6 ns
Operating Temperature (Commercial) — 0C to +70C
Package Type — CPGA-280 (Ceramic Pin Grid Array, 280 pins)
Uri ng Pagpapasok — Through-Hole
Programmability — In-System Programmable (ISP) via JTAG IEEE 1149.1
Technology — CMOS EEPROM, 0.5 um process (MAX third-gen)
Tindminan RoHS — Non-compliant (ceramic CPGA, contains lead)
Katayuan ng Lifecycle — Obsolete (legacy Altera MAX 9000 family)

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