EPM9560GC280-20 vs EPM9560GC280-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560GC280-20 sa pamamagitan ng Altera at EPM9560GC280-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 ObsoletePagsanggunian na paghahambing
| Parametro | EPM9560GC280-20 | EPM9560GC280-15 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EE PLD (CMOS EEPROM-based CPLD) |
| Usable Gates | 12,000 | — |
| Macrocells | 560 | — |
| Maximum User I/O | 212 | — |
| Pin-to-Pin Delay | 20 ns (speed grade -20) | — |
| Counter Frequency (max) | 100 MHz | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) | — |
| I/O Voltage | 3.3 V or 5.0 V configurable | — |
| Process Technology | CMOS EEPROM | — |
| Packhaging | 280-pin CPGA (Ceramic Pin Grid Array) | — |
| Temperature na Operasyon | [DATA_NEEDED: commercial/industrial/military grade] | — |
| In-System Programming | Yes, via IEEE 1149.1 JTAG | — |
| Uri ng Pagpapasok | Through-Hole (CPGA socket) | Through-Hole |
| Tindminan RoHS | [DATA_NEEDED: CPGA package historically contains Pb; likely non-compliant] | Non-compliant (ceramic CPGA, contains lead) |
| Macro Cells | — | 560 |
| Typical Gates | — | 12,000 |
| Maximum Operating Frequency | — | 117.6 MHz |
| Propagation Delay (tpd) | — | 15 ns (speed grade -15) |
| Propagation Delay (alternate datasheet figure) | — | 16.6 ns |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| Operating Temperature (Commercial) | — | 0C to +70C |
| Package Type | — | CPGA-280 (Ceramic Pin Grid Array, 280 pins) |
| Programmability | — | In-System Programmable (ISP) via JTAG IEEE 1149.1 |
| Technology | — | CMOS EEPROM, 0.5 um process (MAX third-gen) |
| Architecture | — | Multiple Array MatriX (MAX) |
| Katayuan ng Lifecycle | — | Obsolete (legacy Altera MAX 9000 family) |