EPM9560RC208-10 vs EPM9560RC208-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC208-10 sa pamamagitan ng Intel at EPM9560RC208-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RC208-10 | EPM9560RC208-15 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macrocells | 560 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/O Pins | 212 (208-pin package variant) | — |
| Usable Gates | 12,000 | 12,000 gates |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: internal toggle frequency in MHz] | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| I/O Standards Supported | 5.0 V TTL, 3.3 V LVTTL, 2.5 V (multiVolt I/O) | — |
| Configuration Memory | EEPROM (in-system programmable via JTAG) | — |
| Process Technology | 0.30 µm CMOS EEPROM | — |
| Temperature na Operasyon | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Packhaging | 208-pin RQFP (Plastic Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Lead-Free | [DATA_NEEDED: confirm lead-free status -10 suffix is conventional Pb-containing] | — |
| Tindminan RoHS | [DATA_NEEDED: not stated in retrieved distributor listings] | [DATA_NEEDED: RoHS status] |
| Programmability | JTAG (IEEE 1149.1) in-system programming | — |
| Macro Cells | — | 560 macro cells |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| Volte ng Pagbibigay | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Speed Grade | — | -15 (15 ns pin-to-pin) |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |