EPM9560RC208-12 vs EPM9560RC208-15C Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC208-12 sa pamamagitan ng Altera at EPM9560RC208-15C sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RC208-12 | EPM9560RC208-15C |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EEPROM-based CPLD | EEPROM-based CPLD (EPLD) |
| Macrocells | 560 | 560 |
| Flip-Flops | 772 | — |
| Usable Gates | 12000 | 12,000 |
| User I/O Lines | 153 | — |
| Propagation Delay (tPD) | 12 ns | 15 ns |
| Maksimum na Taktiko ng Oras | 125 MHz | — |
| Supply Voltage (VCCINT) | 5 V | — |
| I/O Voltage Compatibility | 3.3 V or 5 V | 3.3 V or 5 V |
| Packhaging | 208-pin RQFP (S-PQFP-G208) | 208-pin RQFP |
| Terminal Pitch | 0.50 mm | — |
| Temperature na Operasyon | 0C to +70C (commercial) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| Logic Array Blocks | 20 | — |
| Speed Grade | -12 (12 ns) | -15 (15 ns) |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| User I/O Pins | — | 149 |
| Maximum Counter Frequency | — | 117.6 MHz |
| Supply Voltage Range | — | 4.75 V to 5.25 V |
| Nominal Supply Voltage | — | 5.0 V |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Hanay ng Temperature na Operasyon | — | 0C to +70C (commercial) |
| Logic Architecture | — | Multiple Array MatriX (MAX) third generation |