EPM9560RC208-14 vs EPM9560RC208-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC208-14 sa pamamagitan ng Altera at EPM9560RC208-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RC208-14 | EPM9560RC208-15 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Usable Gates | 12,000 | 12,000 gates |
| Macrocells | 560 | — |
| Logic Array Blocks (LABs) | 16 | — |
| User I/O Pins | 149 | — |
| Maximum Operating Frequency | 117.6 MHz | — |
| Pin-to-Pin Propagation Delay | 14 ns | — |
| Volte ng Pagbibigay | 5 V | 5.0 V |
| I/O Voltage Support | 3.3 V / 5 V | — |
| Program Memory Type | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (JTAG, IEEE 1149.1) | Yes, via IEEE Std. 1149.1 JTAG |
| Packhaging | 208-pin RQFP (PQFP) | 208-pin RQFP (Power Quad Flat Pack) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Process Technology | 0.35 µm CMOS EEPROM | — |
| Tindminan RoHS | Non-compliant (legacy part) | [DATA_NEEDED: RoHS status] |
| Macro Cells | — | 560 macro cells |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| Configuration Technology | — | EEPROM (non-volatile) |
| Temperature na Operasyon | — | [DATA_NEEDED: operating temperature range] |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Speed Grade | — | -15 (15 ns pin-to-pin) |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |