EPM9560RC208-17 vs EPM9560RC208-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC208-17 sa pamamagitan ng Altera at EPM9560RC208-20 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RC208-17 | EPM9560RC208-20 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 9000 | — |
| Product Type | CPLD (EPLD, in-system programmable) | — |
| Usable Gates | 12,000 | 12,000 |
| Macro Cells | 560 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Pin-to-Pin Delay (tPD) | 17 ns | 20 ns |
| Maximum Counter Frequency | 117.6 MHz | — |
| User I/O Pins | 212 | 153 |
| Supply Voltage (VCC) | 5 V | — |
| Packhaging | 208-pin RQFP (RC208) | 208-pin RQFP (28x28 mm) |
| Programming Technology | EEPROM (in-system programmable) | — |
| Program/Erase Cycles | 100 minimum | — |
| JTAG (IEEE 1149.1) Support | Yes | — |
| Architecture | Third-generation MAX (AND-OR PLA) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Device Family | — | MAX 9000 (EPM9560) |
| Macrocells | — | 560 |
| Logic Array Blocks | — | 35 |
| Maksimum na Taktiko ng Oras | — | 100 MHz |
| Volte ng Pagbibigay | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Temperature na Operasyon | — | 0C to +70C (commercial) |
| I/O Standards | — | 5.0 V TTL/CMOS compatible |
| Flip-Flops | — | 772 |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status] |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |