EPM9560RC240-1O vs EPM9560RC240-12 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC240-1O sa pamamagitan ng Intel at EPM9560RC240-12 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9560RC240-1O EPM9560RC240-12
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili Obsolete
Family MAX 9000 MAX 9000 (EPM9560)
Usable Gates 12,000 —
Macrocells 560 560
Logic Array Blocks (LABs) 35 20
Maximum User I/O Pins 216 —
Propagation Delay (tPD) 12 ns (typ, -1 speed grade) —
Global Setup Time (tFSU) 3.0 ns —
Clock-to-Output (tFCO) 4.8 ns —
Maximum Internal Frequency (fCNT) 145 MHz —
Supply Voltage (VCC) 5.0 V —
Operating Temperature (Grade) -40C to +85C (industrial, "-1O" suffix) —
Process Technology CMOS EEPROM, 0.65 um CMOS
Programming In-system programmable via IEEE 1149.1 JTAG —
Architecture Multiple Array MatriX (MAX), third generation —
Packhaging RQFP-240 (240-pin Reduced-height QFP) PQFP-240 (RC240) 0.500 mm pitch, gull-wing
Uri ng Pagpapasok Surface Mount Surface Mount
Tindminan RoHS Compliant (per Altera/Intel product page) [DATA_NEEDED: RoHS compliance]
Lead-Free Yes —
Device Type — EE PLD / CPLD
Flip-Flops — 772
User I/O Pins — 191
Maximum Propagation Delay (tPD) — 13.4 ns
Speed Grade — -12 (13.4 ns tPD)
Maximum Operating Frequency (estimated) — ~76 MHz registered
Core Supply Voltage (VCCINT) — 5 V
I/O Logic Levels — 3.3 V or 5 V (configurable)
Configuration Memory — EEPROM (non-volatile)
Programming Interface — IEEE 1149.1 JTAG
Temperature na Operasyon — [DATA_NEEDED: operating temperature grade]

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