EPM9560RC240-2 vs EPM9560RC240-12 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC240-2 sa pamamagitan ng Altera at EPM9560RC240-12 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RC240-2 | EPM9560RC240-12 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 (EPM9560) |
| Logic Elements | 560 macrocells | — |
| Usable Gates | 12,000 | — |
| Pin-to-Pin Delay | 2 ns (speed grade -2) | — |
| Maximum Frequency | 100 MHz | — |
| Volte ng Pagbibigay | 5 V | — |
| User I/O Count | 212 | — |
| Packhaging | 240-pin RQFP (Metric QFP) | PQFP-240 (RC240) 0.500 mm pitch, gull-wing |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1), in-system programmable | IEEE 1149.1 JTAG |
| Non-Volatile Configuration | Yes (EEPROM-based) | — |
| Temperature na Operasyon | [DATA_NEEDED: commercial/industrial grade] | [DATA_NEEDED: operating temperature grade] |
| Tindminan RoHS | Non-compliant (5V RQFP, pre-RoHS era) | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | No (legacy Sn/Pb process) | — |
| Logic Block Count | [DATA_NEEDED: LAB count] | — |
| Device Type | — | EE PLD / CPLD |
| Macrocells | — | 560 |
| Flip-Flops | — | 772 |
| User I/O Pins | — | 191 |
| Logic Array Blocks (LABs) | — | 20 |
| Maximum Propagation Delay (tPD) | — | 13.4 ns |
| Speed Grade | — | -12 (13.4 ns tPD) |
| Maximum Operating Frequency (estimated) | — | ~76 MHz registered |
| Core Supply Voltage (VCCINT) | — | 5 V |
| I/O Logic Levels | — | 3.3 V or 5 V (configurable) |
| Configuration Memory | — | EEPROM (non-volatile) |
| Process Technology | — | CMOS |