EPM9560RC240-3 vs EPM9560RC240-15YY Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC240-3 sa pamamagitan ng Altera at EPM9560RC240-15YY sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RC240-3 | EPM9560RC240-15YY |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Device Type | Complex Programmable Logic Device (CPLD) | — |
| Family | MAX 9000 | MAX 9000A |
| Macrocells | 560 | — |
| Usable Gates | 12000 | 12,000 |
| Logic Array Blocks (LABs) | 20 | [DATA_NEEDED: LAB count for EPM9560] |
| Pin-to-Pin Propagation Delay | 3 ns (speed grade -3) | — |
| Maximum Operating Frequency | [DATA_NEEDED: fMAX] | 117.6 MHz |
| Supply Voltage (VCCINT) | 5 V | — |
| Supply Voltage (VCCIO) | 5 V | — |
| User I/O Pins | 192 | — |
| Packhaging | 240-pin RQFP (PowerQuad II) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | — |
| Hanay ng Temperature na Operasyon | 0C to +70C (commercial) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS] | Non-RoHS (YY suffix indicates non-compliant / matte tin or SnPb lead finish per Altera legacy convention) |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| Level ng MSL | [DATA_NEEDED: MSL] | — |
| JTAG Support | [DATA_NEEDED: JTAG] | — |
| Logic Type | — | CMOS EEPROM-based CPLD |
| Number of Macrocells | — | 560 |
| Number of User I/O | — | 191 |
| Propagation Delay (tpd) | — | 15 ns |
| Supply Voltage (VCC) | — | 5.0 V |
| Programmability | — | In-system via IEEE 1149.1 (JTAG) |
| Package Type | — | RQFP-240 (Plastic Quad Flat Pack) |
| Temperature na Operasyon | — | 0 C to +70 C (commercial) |
| Speed Grade | — | -15 |