EPM9560RC240-3 vs EPM9560RC240-15YY Comparison
Detailed side-by-side comparison of EPM9560RC240-3 by Altera and EPM9560RC240-15YY by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC240-3 | EPM9560RC240-15YY |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Device Type | Complex Programmable Logic Device (CPLD) | — |
| Family | MAX 9000 | MAX 9000A |
| Macrocells | 560 | — |
| Usable Gates | 12000 | 12,000 |
| Logic Array Blocks (LABs) | 20 | [DATA_NEEDED: LAB count for EPM9560] |
| Pin-to-Pin Propagation Delay | 3 ns (speed grade -3) | — |
| Maximum Operating Frequency | [DATA_NEEDED: fMAX] | 117.6 MHz |
| Supply Voltage (VCCINT) | 5 V | — |
| Supply Voltage (VCCIO) | 5 V | — |
| User I/O Pins | 192 | — |
| Package | 240-pin RQFP (PowerQuad II) | — |
| Mounting Type | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | — |
| Operating Temperature Range | 0C to +70C (commercial) | — |
| RoHS Status | [DATA_NEEDED: RoHS] | Non-RoHS (YY suffix indicates non-compliant / matte tin or SnPb lead finish per Altera legacy convention) |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| MSL Level | [DATA_NEEDED: MSL] | — |
| JTAG Support | [DATA_NEEDED: JTAG] | — |
| Logic Type | — | CMOS EEPROM-based CPLD |
| Number of Macrocells | — | 560 |
| Number of User I/O | — | 191 |
| Propagation Delay (tpd) | — | 15 ns |
| Supply Voltage (VCC) | — | 5.0 V |
| Programmability | — | In-system via IEEE 1149.1 (JTAG) |
| Package Type | — | RQFP-240 (Plastic Quad Flat Pack) |
| Operating Temperature | — | 0 C to +70 C (commercial) |
| Speed Grade | — | -15 |