EPM9560RC304-15 vs EPM9560RC304-15F Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC304-15 sa pamamagitan ng Altera at EPM9560RC304-15F sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM9560RC304-15F - 560-Macrocell MAX 9000 CPLD, 5V, RQFP-304 | Intel
EPM9560RC304-15F ObsoletePagsanggunian na paghahambing
| Parametro | EPM9560RC304-15 | EPM9560RC304-15F |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 9000 | MAX 9000 |
| Architecture | Multiple Array MatriX (MAX), EEPROM-based | Multiple Array MatriX (MAX) with PIA interconnect |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 16 | 16 (40 macrocells each) |
| User I/O Pins | 212 (maximum) | 212 |
| Propagation Delay (tPD) | 15 ns (combinatorial, pin-to-pin) | — |
| Bilang ng Pin | 304 | — |
| Packhaging | 304-pin RQFP (Plastic Quad Flat Pack) | RQFP-304 (304-pin Plastic QFP) |
| Supply Voltage (VCCINT) | 5.0 V | — |
| I/O Standard | 5.0 V TTL / PCI-compliant | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| Technology Node | High-performance CMOS, EEPROM process | — |
| Temperature na Operasyon | [DATA_NEEDED: industrial/commercial temperature grade] | -40C to +85C (industrial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: lead-free / RoHS compliance status] | [DATA_NEEDED: rohs status - not stated in source] |
| Series | — | EPM9560 |
| Usable Gates | — | 12,000 |
| Propagation Delay (tpd) | — | 16.6 ns (max) |
| Maximum Internal Frequency | — | 117.6 MHz |
| Core Supply Voltage | — | 5.0 V |
| Dedicated Inputs | — | 4 |
| Programming Technology | — | 5.0 V in-system EEPROM via JTAG (IEEE 1149.1) |
| Boundary Scan Test (BST) | — | Yes, JTAG-compliant |
| Process Technology | — | High-performance CMOS, EEPROM-based |
| Level ng MSL | — | 3 (168 hours) |