EPM9560RI208-10N vs EPM9560RI208-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RI208-10N sa pamamagitan ng Altera at EPM9560RI208-10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RI208-10N | EPM9560RI208-10 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | CMOS EEPROM-based Multiple Array MatriX (MAX) | — |
| Usable Gates | 12,000 | 12,000 |
| Macro Cells | 560 | — |
| Register Bits | 12,160 | — |
| User I/Os | 212 | — |
| Pin-to-Pin Delay | 10 ns (speed grade -10) | — |
| Maximum Frequency | 100 MHz to 125 MHz | — |
| Volte ng Pagbibigay | 5 V | — |
| Packhaging | 208-pin RQFP (PQFP) | 208-pin RQFP (Power Quad Flat Pack) |
| Temperature na Operasyon | -40C to +85C (Industrial grade, "RI" suffix) | -40 °C to +85 °C (Industrial) |
| Programming Method | In-system via IEEE 1149.1 (JTAG) | — |
| Level ng MSL | 3 (168 Hours) | — |
| Tindminan RoHS | ROHS3 Compliant (per fpgalink) | ROHS3 Compliant |
| Configuration Memory | On-chip EEPROM (non-volatile) | EEPROM, 100 erase/program cycles |
| Macrocells | — | 560 |
| Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 144 MHz |
| Supply Voltage (VCCINT) | — | 5.0 V |
| User I/O Pins | — | 212 (typical for 208-RQFP package) |
| Uri ng Pagpapasok | — | Surface Mount |
| Programming Interface | — | IEEE 1149.1 (JTAG) / ISP |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | — | 3 (168 Hours) |
| Lead Time | — | 1-7 days (per fpgalink listing) |