EPM9560RI208-15 vs EPM9560RI208-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RI208-15 sa pamamagitan ng Intel at EPM9560RI208-10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RI208-15 | EPM9560RI208-10 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Family | MAX 9000 | MAX 9000 |
| Architecture | CMOS EEPROM-based Multiple Array MatriX (MAX) | — |
| Macrocells | 560 | 560 |
| Typical Usable Gates | 12,000 | — |
| User I/Os | 153 | — |
| Internal Frequency (max) | 145 MHz | — |
| Propagation Delay (tPD) | 11.4 ns (commercial); 15 ns speed grade | — |
| Logic Family | CMOS | — |
| Bilang ng Pins | 208 | — |
| Package Code | HFQFP (Power Quad Flat Pack, gull-wing) | — |
| Package Type | RQFP-208 | — |
| Supply Voltage (VCC) | 5 V nominal (4.5 V to 5.5 V) | — |
| I/O Voltage Support | 3.3 V or 5 V multi-volt I/O | — |
| Temperature na Operasyon | 0 °C to 70 °C (industrial grade; per package suffix R) | -40 °C to +85 °C (Industrial) |
| In-System Programmability | Yes (JTAG / IEEE 1149.1) | — |
| Boundary-Scan (JTAG) | Compliant | — |
| Configuration Memory | On-chip EEPROM (non-volatile) | EEPROM, 100 erase/program cycles |
| Tindminan RoHS | ROHS3 Compliant | ROHS3 Compliant |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | 3 (168 hours) | 3 (168 Hours) |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 12,000 |
| Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 144 MHz |
| Supply Voltage (VCCINT) | — | 5.0 V |
| User I/O Pins | — | 212 (typical for 208-RQFP package) |
| Packhaging | — | 208-pin RQFP (Power Quad Flat Pack) |
| Uri ng Pagpapasok | — | Surface Mount |
| Programming Interface | — | IEEE 1149.1 (JTAG) / ISP |
| Lead Time | — | 1-7 days (per fpgalink listing) |