EPM9560RI208-15 vs EPM9560RI208-20N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RI208-15 sa pamamagitan ng Intel at EPM9560RI208-20N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RI208-15 | EPM9560RI208-20N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 9000 | — |
| Architecture | CMOS EEPROM-based Multiple Array MatriX (MAX) | — |
| Macrocells | 560 | 560 |
| Typical Usable Gates | 12,000 | — |
| User I/Os | 153 | — |
| Internal Frequency (max) | 145 MHz | — |
| Propagation Delay (tPD) | 11.4 ns (commercial); 15 ns speed grade | — |
| Logic Family | CMOS | — |
| Bilang ng Pins | 208 | — |
| Package Code | HFQFP (Power Quad Flat Pack, gull-wing) | — |
| Package Type | RQFP-208 | — |
| Supply Voltage (VCC) | 5 V nominal (4.5 V to 5.5 V) | — |
| I/O Voltage Support | 3.3 V or 5 V multi-volt I/O | — |
| Temperature na Operasyon | 0 °C to 70 °C (industrial grade; per package suffix R) | Industrial (-40C to +85C) |
| In-System Programmability | Yes (JTAG / IEEE 1149.1) | Yes, via IEEE Std. 1149.1 JTAG |
| Boundary-Scan (JTAG) | Compliant | — |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| Tindminan RoHS | ROHS3 Compliant | [DATA_NEEDED: RoHS status] |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | 3 (168 hours) | — |
| Device Family | — | MAX 9000 |
| Usable Gates | — | 12,000 |
| Pin-to-Pin Delay | — | 20 ns (-20 speed grade) |
| Counter Speed | — | 100 MHz |
| Volte ng Pagbibigay | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| Packhaging | — | 208-pin RQFP |
| Uri ng Pagpapasok | — | Surface Mount |
| Development Tool | — | MAX+PLUS II |
| Design Entry | — | Schematic, VHDL, Verilog HDL, AHDL |
| Packaging | — | Tray |
| Logic Architecture | — | Third-generation MAX (Multiple Array MatriX) |
| Fabrication Process | — | Advanced CMOS |