EPM9560RI208-15N vs EPM9560RI205-15 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RI208-15N sa pamamagitan ng Altera at EPM9560RI205-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9560RI208-15N EPM9560RI205-15
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Manufacturer Altera (Intel Programmable Solutions Group) —
Device Family MAX 9000 —
Device Type EPLD (Erasable Programmable Logic Device) —
Architecture Multiple Array MatriX (MAX), 3rd generation —
Configuration Memory CMOS EEPROM, in-system programmable —
Packhaging 208-pin RQFP (Ruggedized Quad Flat Pack) RQFP-205 (PowerQuad4)
Total Pins 356 (per third-party catalog; see _validation_note) —
Package Pin Count 208 —
Terminal Form Gull Wing —
Package Code HFQFP —
User I/Os 216 (per DigiChip specification; see _validation_note) —
Maximum Internal Frequency 145 MHz —
Propagation Delay (tPD) 11.4 ns (15 ns speed grade) —
Speed Grade -15 -15 (15 ns pin-to-pin delay)
Volte ng Pagbibigay 5.0 V —
Temperature na Operasyon 0C to 70C (Commercial) -40 C to +85 C (industrial)
Temperature Grade Industrial (per Vyrian/Partstack listings) —
Logic Family CMOS —
Programming Interface IEEE 1149.1 JTAG, 5.0-V in-system —
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: rohs_compliance]
Family — MAX 9000
Device — EPM9560
Logic Capacity — 6,000 usable gates
Macrocells — 212
Logic Array Blocks (LABs) — 20
Maximum User I/O Pins — 164
Propagation Delay (tpd) — 15 ns
Supply Voltage (VCC) — 5.0 V
Technology — CMOS EEPROM
In-System Programmability — Yes (IEEE 1149.1 JTAG)
Uri ng Pagpapasok — Surface Mount

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