EPM9560RI208-15N vs EPM9560RI208-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RI208-15N sa pamamagitan ng Altera at EPM9560RI208-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RI208-15N | EPM9560RI208-10N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Manufacturer | Altera (Intel Programmable Solutions Group) | — |
| Device Family | MAX 9000 | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | Multiple Array MatriX (MAX), 3rd generation | CMOS EEPROM-based Multiple Array MatriX (MAX) |
| Configuration Memory | CMOS EEPROM, in-system programmable | On-chip EEPROM (non-volatile) |
| Packhaging | 208-pin RQFP (Ruggedized Quad Flat Pack) | 208-pin RQFP (PQFP) |
| Total Pins | 356 (per third-party catalog; see _validation_note) | — |
| Package Pin Count | 208 | — |
| Terminal Form | Gull Wing | — |
| Package Code | HFQFP | — |
| User I/Os | 216 (per DigiChip specification; see _validation_note) | 212 |
| Maximum Internal Frequency | 145 MHz | — |
| Propagation Delay (tPD) | 11.4 ns (15 ns speed grade) | — |
| Speed Grade | -15 | — |
| Volte ng Pagbibigay | 5.0 V | 5 V |
| Temperature na Operasyon | 0C to 70C (Commercial) | -40C to +85C (Industrial grade, "RI" suffix) |
| Temperature Grade | Industrial (per Vyrian/Partstack listings) | — |
| Logic Family | CMOS | — |
| Programming Interface | IEEE 1149.1 JTAG, 5.0-V in-system | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | ROHS3 Compliant (per fpgalink) |
| Family | — | MAX 9000 |
| Usable Gates | — | 12,000 |
| Macro Cells | — | 560 |
| Register Bits | — | 12,160 |
| Pin-to-Pin Delay | — | 10 ns (speed grade -10) |
| Maximum Frequency | — | 100 MHz to 125 MHz |
| Programming Method | — | In-system via IEEE 1149.1 (JTAG) |
| Level ng MSL | — | 3 (168 Hours) |